To perform an over voltage stress test (OVST) on a high-side PMOS in a current mirror configuration, the gate of the PMOS device must be raised to a high voltage using a probe pad and the current into the gate of the device must be measured. To accurately measure gate current, the DC current into all other components connected to the gate node must be very low (ideally zero). The two-fold problem is that all components connected to the gate node must be able to withstand a high DC voltage and must not provide any current paths from the node.
A basic prior art PMOS current mirror is shown in FIG. 1. The circuit of FIG. 1 includes PMOS transistors Mp2 and Mp3; NMOS transistors Mn3 and Mn1; voltage nodes Vgp, Vdd, Vout, Vcc3, and Von; and output current Iout. When considering the basic prior art PMOS current mirror, as shown in FIG. 1, the problem specifically is when the voltage on node Vgp is raised above node Vdd. In this case, the parasitic diode from the drain to the well of device Mp2 is activated, providing a significant current path from node Vgp to source node Vdd and making OVST impossible.